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အလည္ လာသြားသူမ်ား


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Ram မ်ားႏွင့္ မိတ္ဆက္ျခင္း

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SDRAM ေလးပါ

/CS/RAS/CAS/WEBAnA10AnCommand
HxxxxxxCommand inhibit (No operation)
LHHHxxxNo operation
LHHLxxxBurst Terminate: stop a burst read or burst write in progress.
LHLHbankLcolumnRead: Read a burst of data from the currently active row.
LHLHbankHcolumnRead with auto precharge: As above, and precharge (close row) when done.
LHLLbankLcolumnWrite: Write a burst of data to the currently active row.
LHLLbankHcolumnWrite with auto precharge: As above, and precharge (close row) when done.
LLHHbankrowActive (activate): open a row for Read and Write commands.
LLHLbankLxPrecharge: Deactivate (close) the current row of selected bank.
LLHLxHxPrecharge all: Deactivate (close) the current row of all banks.
LLLHxxxAuto refresh: Refresh one row of each bank, using an internal counter. All banks must be precharged.
LLLL0 0modeLoad mode register: A0 through A9 are loaded to configure the DRAM chip.
The most significant settings are CAS latency (2 or 3 cycles) and burst length (1, 2, 4 or 8 cycles)


DDR SDRAM ေလးပါ

 

Standard nameMemory clock
(MHz)
Cycle time[4]
(ns)
I/O bus clock
(MHz)
Data rate
(MT/s)
VDDQ
(V)
Module namePeak transfer rate
(MB/s)
Timings
(CL-tRCD-tRP)
DDR-200100101002002.5±0.2PC-16001600
DDR-266133⅓7.5133⅓266⅔PC-21002133⅓2.5-3-3
DDR-333166⅔6166⅔333⅓PC-27002666⅔
DDR-400A
DDR-400B
DDR-400C
20052004002.6±0.1PC-320032002.5-3-3
3-3-3
3-4-4



















Mobile DDR ေလးပါ


CKCA0
(RAS)
CA1
(CAS)
CA2
(WE)
CA3CA4CA5CA6CA7CA8CA9Operation
HHHNOP
HHLHHPrecharge all banks
HHLHLBA2BA1BA0Precharge one bank
HHLHA30A31A32BA2BA1BA0Preactive
(LPDDR2-N only)
A20A21A22A23A24A25A26A27A28A29
HHLLBurst terminate
HLHreservedC1C2BA2BA1BA0Read
(AP=auto-precharge)
APC3C4C5C6C7C8C9C10C11
HLLreservedC1C2BA2BA1BA0Write
(AP=auto-precharge)
APC3C4C5C6C7C8C9C10C11
LHR8R9R10R11R12BA2BA1BA0Activate
(R0–14=Row address)
R0R1R2R3R4R5R6R7R13R14
LHA15A16A17A18A19BA2BA1BA0Activate
(LPDDR2-N only)
A5A6A7A8A9A10A11A12A13A14
LLHHRefresh all banks
(LPDDR2-Sx only)
LLHLRefresh one bank
(Round-robin addressing)
LLLHMA0MA1MA2MA3MA4MA5Mode register read
(MA0–7=Address)
MA6MA7
LLLLMA0MA1MA2MA3MA4MA5Mode register write
(OP0–7=Data)
  
MA6MA7OP0OP1OP2OP3OP4OP5OP6OP7







DDR2 SDRAM ေလးပါ








File:1GB DDR2 SO-DIMM.png








Standard name
Memory clock (MHz)
Cycle time (ns)
I/O bus clock (MHz)
Data rate (MT/s)
Module name
Peak transfer rate (MB/s)
Timings[2][3](CL-tRCD-tRP)
CAS latency(ns)
DDR2-400B
DDR2-400C
10010200400PC2-320032003-3-3
4-4-4
15  
20  
DDR2-533B
DDR2-533C
133⅓266⅔533⅓PC2-4200*4266⅔3-3-3
4-4-4
11¼
15  
DDR2-667C
DDR2-667D
166⅔6333⅓666⅔PC2-5300*5333⅓4-4-4
5-5-5
12  
15  
DDR2-800C
DDR2-800D
DDR2-800E
2005400800PC2-640064004-4-4
5-5-5
6-6-6
10  
12½
15  
DDR2-1066E
DDR2-1066F
266⅔533⅓1066⅔PC2-8500*8533⅓6-6-6
7-7-7
11¼
13⅛  
                                                                   

DDR3 SDRAM ေလးပါ

 
         File:4GB DDR3 SO-DIMM.jpg    
Standard name
Memory clock (MHz)
Cycle time (ns)
I/O bus clock (MHz)
Data rate (MT/s)
Module name
Peak transfer rate (MB/s)
Timings (CL-tRCD-tRP)
CAS latency (ns)
DDR3-800D
DDR3-800E
10010400800PC3-640064005-5-5
6-6-6
12 12
15  
DDR3-1066E
DDR3-1066F
DDR3-1066G
133⅓7 12533⅓1066⅔PC3-85008533⅓6-6-6
7-7-7
8-8-8
11 14
13 18
15  
DDR3-1333F*
DDR3-1333G
DDR3-1333H
DDR3-1333J*
166⅔6666⅔1333⅓PC3-1060010666⅔7-7-7
8-8-8
9-9-9
10-10-10
10 12
12  
13 12
15  
DDR3-1600G*
DDR3-1600H
DDR3-1600J
DDR3-1600K
20058001600PC3-12800128008-8-8
9-9-9
10-10-10
11-11-11
10  
11 14
12 12
13 34
DDR3-1866J*
DDR3-1866K
DDR3-1866L
DDR3-1866M*
233⅓4 27933⅓1866⅔PC3-1490014933⅓10-10-10
11-11-11
12-12-12
13-13-13
10 57
11 1114
12 67
13 1314
DDR3-2133K*
DDR3-2133L
DDR3-2133M
DDR3-2133N*
266⅔3 341066⅔2133⅓PC3-1700017066⅔11-11-11
12-12-12
13-13-13
14-14-14
10 516
11 14
12 316
13 18 
                                  

DDR4 SDRAM ေလးပါ

 
         File:Samsung displays first DDR4 module.jpg
SBGn, BAn/ACTA17A16
/RAS
A15
/CAS
A14
/WE
A13A12A11A10A9–0Command
H— x —Deselect (No operation)
LbankLRow addressActive (activate): open a row
LxHxHHH— x —No operation
LxHxHHLxlongxZQ Calibration
LbankHxHLHxBCxAPColumnRead (BC=burst chop)
LbankHxHLLxBCxAPColumnWrite (AP=auto-precharge)
LxHxLHH— x —(Unassigned, reserved)
LxHxLHLxHxPrecharge all banks
LbankHxLHLxLxPrecharge one bank
LxHxLLH— x —Refresh
LregisterH0LLL0dataMode register set (MR0–MR6)
             



  
   

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